Soft errors occur in logic circuit nodes (e.g., timing logic, arithmetic circuits), in storage circuit nodes (e.g., register files, sequentials, latches, RAM cells), and in other circuits having digital nodes, as a result of ambient radiation impacting the transistors that make up the circuits. For example, they can cause a stored '1 to become a '0 and a stored '0 to become a '1. Unfortunately, reducing Soft Error Rates (SER) in contemporary integrated circuits such as processors can be costly in terms of power and area. For example, typical state element radiation hardening methodologies (e.g., using redundant circuitry) may have a greater than 2× power and area cost. Current radiation hardening approaches generally depend on redundant storage, and interlocking schemes. Such approaches tend to be inherently costly, both because of increased transistor count, and the need for physical separation of vulnerable diffusions. Accordingly, new design approaches that are less area and power costly are desired.